Explorer: the diamond-wafer framework's equations, live. Pick your reading level in each panel.
New here? Take the guided tour: eight steps from why diamond, through power circuits, to a room-temperature quantum computer.
1 · Why diamond? Four scorecards
Engineers rank semiconductors with figures of merit. Move the switch to see diamond scored with holes (what can be built today) or electrons.
Each bar says how many times better than silicon a material is at one job. Diamond's bars are the tallest, sometimes by tens of thousands.
BFOM = εμEc³ scores conduction loss in a power switch; BHFFOM = μEc² switching loss; JFOM the power–frequency product; KFOM the heat-limited switching density. The log axis hides how extreme diamond's 10 MV/cm breakdown field is: it enters cubed.
Values are room-temperature single-crystal numbers with diamond mobilities at the ultrapure upper bound; the figures assume full dopant ionization, which fails in diamond (panel 3), so read them as ceilings and pair them with panel 2's measured points.
2 · Power switches: the limit lines and where real diamond sits
Lower is better. The stars are real diamond transistors; the gap to the teal line is the room left to improve.
Every line is the best a material could ever do. The stars are what people have actually built with diamond. They already beat silicon's best-possible line.
Ron,sp = 4BV²/(εμEc³) for a one-sided drift region. The measured 2022 device beats ideal silicon by about 90× and trails ideal SiC; a vertical diamond device at 1% of its own limit would match GaN.
Measured points are lateral hydrogen-terminated NO₂-doped MOSFETs on heteroepitaxial wafers; the 3659 V device's Ron is derived from its reported Baliga figure of merit. SiC's T2.4 mobility law is applied to its limit line; diamond's bulk-doped Ron falls with temperature instead (chapter E9).
Boron in silicon gives up its hole easily. Boron in diamond holds on. Slide the doping level.
Adding impurity atoms is how you make a semiconductor conduct. In diamond most of those atoms just sit there at room temperature. Heat wakes them up.
Charge neutrality with a single acceptor level EA: p(p+ND)/(NA−ND−p) = (NV/g)e−EA/kT. Boron at 0.37 eV and phosphorus at 0.57 eV are 8 to 13 kT deep at 300 K.
Effective mass 0.8 m0, degeneracy 4, no compensation. Above about 3×1020 cm⁻³ the boron band merges with the valence band and the model no longer applies (metallic conduction, superconductivity). Surface transfer doping sidesteps activation entirely (chapter 3).
4 · The qubit's fingerprint: optically detected magnetic resonance
Shine green light, sweep microwaves, watch the red glow dip. The dips move with the magnetic field, which is why a diamond chip is also a compass.
The NV center glows red. When a microwave hits exactly its note (2.87 GHz), the glow dims a little. A magnet splits that note into two, and the crystal has four kinds of NV pointing different ways, so you can see up to eight dips.
H/h = D(Sz² − 2/3) + γeB·S with D = 2.870 GHz and γe = 28 MHz/mT. Each of the four ⟨111⟩ orientations sees a different projection B∥, giving lines at D ± γeB∥.
Second-order perpendicular shift 3γ²B⊥²/(2D) included; hyperfine structure (2.16 MHz for ¹⁴N) omitted at these line widths. Contrast fixed at 7.5% per orientation for an ensemble. The Python package includes the hyperfine term.
5 · Two qubits talking: distance, coherence, and the real bottleneck
Magnetic coupling fades as 1/r³. Slide coherence and preparation probability and see which one actually limits the gate.
Two qubits feel each other through magnetism, but only when very close. The surprise: even with perfect memory, the gate fails if the qubit was not set up right at the start (that is the q slider).
ν = 52 MHz·nm³/r³; gate time 1/(2ν); with a spin echo the coherence factor is w = exp(−(t/T₂)³) and the Bell fidelity is q²(1+w)²/4 + (1−q²)/4.
With the published pair's parameters (25 nm, 19.7 kHz double-quantum coupling, T₂ 150 and 514 µs) the coherence-limited fidelity is 0.998; the measured 0.67 corresponds to q ≈ 0.75, the NV⁻ charge fraction under green light. See chapter E5, sections E5.1b and E5.1c.
6 · A real converter: diamond against silicon carbide and gallium nitride
Pick an application. Loss per switch at the optimum die area scales as √(R·C·f).
A power switch wastes energy two ways: resistance while on, and charging its own capacitance every time it flips. The best material wastes the least of both.
Pmin = 2IV√(fRon,spCoss,sp/2) with Coss,sp ≈ εEc/(2BV). Gate charge, reverse recovery, and GaN dynamic Ron are not modeled.
Hard-switched half-bridge, duty 0.5, area-optimized per switch. The measured diamond curve scales the 2022 device's Ron,sp as BV² to the chosen voltage class. Ideal diamond is a ceiling; today's device beats ideal silicon and trails ideal SiC. Chapter E9.
8 · Error correction: which error rates let a bigger code help?
Precomputed Monte Carlo of the surface code with a matching decoder (in-cell error fixed at 0.1%). Pick the code distance.
Quantum computers fix their own mistakes by spreading one answer over many qubits, like voting. That only works if each qubit and each connection is already pretty good. Green squares are where adding more qubits makes things better.
Planar surface code, phenomenological noise, minimum-weight perfect matching. Data error per round = in-cell error + 4·(8/15)·link error; measurement error = readout error + the same link term. Break-even (black dashed line): link error of about 1.3% per gate.
2000 shots per point, so entries below about 5×10⁻⁴ are upper limits and the green corner is noisy. The mapping from hardware rates to the two phenomenological rates is first order; hook errors and slow-readout idling need the circuit-level model X-1b. Validation: equal data and readout error crosses at 3.1% versus the published 2.93% (chapter E6).
9 · How big is a room-temperature quantum computer?
Slide the error-correction cycle time (set by readout) and the cell yield.
Even a giant quantum computer would fit on a fingernail of diamond. The problem is speed: reading a diamond qubit takes about a thousand times longer than a superconducting one, so big jobs take years instead of hours.
Physical qubits from published surface-code estimates; 4 qubits per NV cell; time scales linearly with the cycle. Area is never the constraint; readout time and yield are.
Wall-clock times assume the published qubit counts at 10⁻³ physical error and a 1 µs reference cycle. Electrical readout (proposed, 100 µs) would bring a year down to a month. Chapter E10.